The present invention relates to arrays for performing logic functions such as a programmable logic array (PLA). More particularly, it relates to the powering of such arrays for performing logic functions.
The performing of logic in matrices of identical circuit elements each located at a unique intersection of input and output lines is well known. One well known arrangement for doing this is referred to as a programmable logic array or PLA. In Cox et al U.S. Pat. No. 3,987,287, assigned to the present assignee, a PLA is described in which an input signal is fed to decoders which generate min-terms and feed them to a first array called a product term generator or an AND array. The outputs of this AND array or the product terms are fed to a second array called the sum of product term generator or OR array. The outputs of the OR array are then fed to latches so that they can be used at a later time as inputs to the same PLA in performing a second logic function.
In the past the powering of the arrays has been done in a number of ways. One such scheme for powering is to statically power the AND array and OR array. That is, once the PLA is powered up the AND arrays or OR arrays are powered continuously with excitation voltage whether they are performing a logical function or not. Of course this consumes significant amounts of power so that schemes for the dynamic powering of the arrays have been used. In such dynamic powering schemes, either or both of the arrays are usually maintained in an off power state until they are ready to use. Then a clock signal is fed to the array and activates switches that allow power to reach the arrays in the PLA. Dynamic powering of both the AND and OR arrays would appear to offer the lowest power consumption. However, even with dynamic powering schemes the arrays may not perform useful logic functions each time they are powered up. Furthermore, with such schemes the benefits of dynamic powering are partially offset by the additional circuitry required for the generating of the multiple overlapping clock signals needed for such powering. In addition, when it is desired to place two or more PLAs on the same chip having different timing and performance requirements the complex circuitry needed on the generation of the clock signals makes it impractical to implement dynamically powered AND and OR arrays in all the PLAs on the chip. Therefore as a compromise, the AND arrays have been dynamically powered while the OR arrays are statically powered; thereby obtaining partial benefits of dynamic powering while avoiding the complexities of dynamically powering both AND and OR arrays.
In Henle U.S. Pat. No. 3,599,182, assigned to the same assignee as the present application, it is suggested that decoders for a memory cell be dynamically powered. Here the decoder is split into halves and the first half of the decoder is powered all of the time while only a portion of the second half of the decoder is energized after the first half of the decoder is assessed and it is apparent that that portion of the second half will be used. Thus the Henle patent describes the technique of using the inputs of the signals to energize the decoders associated with memory arrays.